Such a differential amplifier is known, inter alia from European Patent Application EP 0,325,299, in particular FIG. 1 thereof, and from an article "A Transistor-Only Current-Mode Sigma Delta Modulator", S. J. Daubert et al, IEEE Journal of Solid State Circuits, Vol. 27, No. 5, May 1992, pp. 821-830, in particular FIG. 6 thereof. In the differential amplifier disclosed in said European Patent Application the first (MN101) and the second (MN102) transistor of the differential pair are coupled to the output terminals (107/108) via a first set of cascode transistors (MP101) and the third (MN105) and the fourth (MN206) transistor are coupled to the output terminals via a second set of cascode transistors (MN103/MN104). In the differential amplifier known from the article the first (M1) and the second (M2) transistor of the differential pair and the third (M20) and the fourth (M21) transistor are coupled to the output terminals (outp/outn) via the same set of cascode transistors (M16/M17). However, in both prior-art differential amplifiers the first main electrodes of the third and the fourth transistor are interconnected, the node thus formed being connected to the supply terminal via the parallel-connected main current paths of the fifth and the sixth transistor. The third and the fourth transistor are arranged as a current source and present a high-impedance load to the first and the second transistor of the differential pair. At the output terminals the differential pair produces output voltages whose common-mode component is suppressed by means of the fifth and the sixth transistor, which are operated as controllable resistances and which have their control electrodes coupled to the output terminals for controlling the resistance. In the prior-art differential amplifiers a simultaneous increase of the output voltages will cause the resistance of the fifth and the sixth transistor to decrease simultaneously, as result of which the voltage on the node between the third and the fourth transistor will decrease. Since the control electrodes of the third and the fourth transistor are connected to a fixed reference voltage the decrease of the voltage on the node will cause the current in the third and the fourth transistor to increase. This current increase compensates for the common-mode increase of the output voltages. The differential-mode component of the output voltages is not affected because in that case the resistance increase of, for example, the fifth transistor is cancelled by the resistance decrease of the sixth transistor, as a result of which the parallel resistance of the fifth and the sixth transistor remains virtually constant.
The third and the fourth transistor each introduce a noise current in the output terminals. It may be assumed that the noise current is caused by an equivalent noise voltage source in series with the control electrodes of the third and the fourth transistor. At the output terminals the equivalent noise voltage source of the third transistor produces a differential noise current whose magnitude is determined inter alia by the impedance effectively seen by the second main electrode of the third transistor. This impedance is equal to approximately twice the inverse of the transconductance of the third transistor because the first main electrodes of the third and the fourth transistor are interconnected. The same applies to the differential noise current caused by the fourth transistor. The effective impedance is comparatively low and the differential noise contribution of the third and the fourth transistor to the output signal of the prior-art differential amplifier is comparatively high. Increasing the effective impedance by arranging additional resistors in series with the first main electrodes of the third and the fourth transistor does reduce the gain of the noise voltage on the control electrodes of these transistors but it also reduces the effect of the common-mode rejection of the fifth and the sixth transistor operating as a controllable resistance.